1. Field of the Invention
The invention relates to a reference ladder circuit, particularly to a reference ladder circuit for use with an analog/digital converter (ADC).
2. Description of the Related Art
Many common analog/digital converter (ADC) architectures, notably Flash converters and Folding & Interpolating converters include a circuit stage—called reference ladder in the present document—comparing an analog input voltage to a set of constant reference voltages. The constant reference voltages are typically linearly spaced across the input voltage range supported by the ADC. The reference ladder typically includes a circuit generating the reference voltages and a set of differential amplifiers computing the differences between an input voltage and each reference voltage.
None of the reference ladder implementations published so far possesses all the properties of: (a) The input signal propagates to the outputs of all differential amplifiers with essentially the same delay, (b) The implementation is fully differential and (c) The reference voltages are not perturbed by the input bias current of the differential amplifiers.
Indeed, at the sampling rates and resolutions where existing ADC chips operate, satisfactory ADC performance can be achieved even if the reference ladder lacks some of these features. However, as sampling rates increase well above 1 GS/s, the above features become increasingly necessary for the following reasons: (a) Delay mismatch (a.k.a. skew) between differential amplifier outputs must remain a small fraction of the sampling period. (b) As sampling rates increase, delay matching specifications become increasingly stringent. As transistors become faster, their breakdown voltage tends to decrease. Therefore, ADC implementations pushing the speed limit must operate with ever smaller signal swings. A fully differential architecture reduces the voltage swing seen by a differential amplifier input by half compared to a single-ended or pseudo-differential architecture.
The reference ladder implementation most commonly described is depicted in FIG. 1. The input voltage Vin is applied to one input of each differential amplifier. The other amplifier input is connected to the reference voltage produced by a chain of equal resistors R. Two reference voltages Vmin and Vmax are applied to the endpoints of the chain. They define the boundaries of the reference voltage range. Intermediate nodes of the chain will settle to linearly spaced intermediate voltages, to the extent that the differential amplifier inputs draw only negligible current.
In practice, if the differential amplifiers are implemented using bipolar transistors in the input stage, they draw a substantial signal-dependent DC input current, which tends to distort the distribution of reference voltages. In order to minimize this effect, the value of resistors R must be chosen small enough that the DC current through the chain is much larger than the input currents of the differential amplifiers. This sensitivity to amplifier input currents is a drawback of this circuit.
The other drawback is that the circuit is single-ended. It is possible to obtain a pseudo-differential version of this circuit by combining two of them, but this solution does not lead to a reduction in input signal swing because one input of each differential amplifier remains a DC voltage.
A truly differential reference ladder implementation has been described in J. Lee, P. Roux, U. V. Koc, T. Link, Y. Baeyens, Y. K. Chen, “A 5-b 10-GSample/s A/D Converter for 10-Gb/s Optical Receivers”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 10, October 2004, pp. 1671-1679. This circuit is shown in FIG. 2. Input Vinp is the positive side and Vinn the negative side of a differential input voltage. By means of two chains of resistors R across which flows a reference current Iref, a number of intermediate signals are obtained. The intermediate signals are identical to Vinp and Vinn except for a DC offset determined by R and Iref. In this circuit, the two inputs of each differential amplifier vary in a complementary fashion. Thereby, for a same differential input voltage range seen at the amplifier inputs, the voltage swing at inputs Vinp and Vinn is a factor of two smaller than in the previous circuit. This feature enables significant reduction of nonlinear distortion if the input signal amplitude would otherwise cause the active devices to operate near the limit of their breakdown voltage.
A substantial drawback of the differential reference ladder circuit shown in FIG. 2 is that the input signal must propagate down a chain of resistors. Because of the input capacitance of the differential amplifiers, the signal gets delayed and low-pass filtered as it travels down the chain. The delay from the input to each differential amplifier output depends on the number of resistors on the signal path to this particular amplifier. Thereby, the delay between the positive and the negative side of a same differential amplifier cannot be well matched. Also, skew between the outputs of different amplifiers is unavoidable. For these reasons, the above circuit cannot be used in practice for very high-speed ADC.
It can be shown that input bias currents of the differential amplifier will affect the accuracy and linearity of the above reference ladder circuit to a similar extent as the circuit in FIG. 1.